1. Field of the Invention
The present invention relates to AC coupling capacitors and, in particular, to a circuit for maintaining the bias voltage across a coupling capacitor when power has been removed.
2. Description of the Related Art
Many battery-powered or low-powered electronic circuits are only required to operate for short periods of time and are, therefore, typically turned off when their operation is not required. In some applications, a significant period of time may elapse between each required operation.
When a low-powered circuit includes a DC-biased AC coupling capacitor, care must be taken to insure that once turned off, the circuit will be ready to perform its required operation as soon as the circuit is turned back on again. With a DC-biased AC coupling capacitor, DC bias voltages generated by the circuit control the charge on the capacitor.
Often when a circuit is powered down, there is a change in the DC bias voltages generated by the circuit. Thus, when the DC bias voltages change, the charge stored on the coupling capacitor also changes. Therefore, when the circuit is powered back on, a substantial charge recovery time may be required to restore the original charge. Ideally, any required charge recovery time should be very short, thereby permitting the circuit to be powered on just prior to performing its required operation.
FIG. 1 shows a schematic diagram of a conventional low-powered circuit 10 which illustrates the operation of a DC-biased AC coupling capacitor. As shown in FIG. 1, circuit 10 includes a coupling capacitor stage 12 that passes a pair of output differential DC-biased AC signals Vout+ and Vout- in response to a pair of input differential DC-biased AC signals Vin+ and Vin- and a DC bias voltage Vb.
Circuit 10 also includes a source stage 14 that generates the input AC signals Vin+ and Vin-. The input AC signals Vin+ and Vin- are generated at the emitters of transistors Q3 and Q4, respectively, in response to a pair of intermediate differential DC-biased AC signals Vm+ and Vm- received at the bases of transistors Q3 and Q4. Transistors Q3 and Q4, which function as emitter followers, reproduce the intermediate AC signals Vm+ and Vm- at the emitters of transistors Q3 and Q4, respectively, with only a change in the DC bias level.
The intermediate AC signals Vm+ and Vm- are formed by combining a pair of externally-generated differential AC signals, introduced into circuit 10 by signal generators A1 and A2, respectively, with a signal bias voltage Vs. The signal bias voltage Vs is generated at node N1 in response to a collector current Ic2 sunk by transistor Q2 through resistor R2.
Circuit 10 further includes a biasing stage 16 that generates the DC bias voltage Vb. In operation, the output AC signals Vout+ and Vout- are DC biased by the DC bias voltage Vb. The bias DC voltage Vb is generated at the emitter of transistor Q6 in response to an intermediate voltage Vi received at the base of transistor Q6. Transistor Q6, which also functions as an emitter follower, reproduces the intermediate voltage Vi at the emitter of transistor Q6 with only a change in the DC bias level. As shown in FIG. 1, the intermediate voltage Vi is generated in response to the simple voltage divider formed by resistors R6 and R9.
When switches SW1 and SW4 are closed and switches SW2 and SW3 are open, thereby powering on circuit 10, a bias voltage exists across capacitors C1 and C2 as a result of the DC bias of the input AC signals Vin+ and Vin- and the DC bias voltage Vb. When switches SW1 and SW4 are open, thereby powering off circuit 10, current no longer flows in resistors R1, R2, R6 and R9. The voltage at node N1 drops towards ground as does the voltage at nodes N4 and N5. Consequently, the current in transistors Q3 and Q4 drops to zero, thereby powering off circuit 10.
FIG. 2 shows a schematic diagram of a circuit which is electrically equivalent to circuit of FIG. 1 in a powered off condition. As shown in FIG. 2, in the powered off condition, the bias voltage across capacitors C1 and C2 bleeds off because resistors R3, R4, R5, R7 and R8 are effectively connected across capacitors C1 and C2. Recovery from the powered off condition requires that the lost charge on capacitors C1 and C2 be restored. The amount of time required for this recovery depends on how much charge was lost and the value of the RC time constant.
In the past, some designs have attempted to reduce this recovery time by temporarily reducing the R of the RC time constant. As shown in FIG. 1, this technique is implemented by using switches SW2 and SW3. During the recovery time switches SW2 and SW3 are closed. The recovery time of capacitors C1 and C2 is then limited by the sink and source capabilities of transistors Q3, Q4, and Q6, and the real world resistance of switches SW2 and SW3.
These real world constraints place a lower limit on the recovery time using this technique. Furthermore, a switch control circuit (not shown), which adds complexity and power dissipation to the design, is required to open and close switches SW2 and SW3. Thus, there is a need for a circuit which maintains the bias voltage across a coupling capacitor during a powered off condition, thereby eliminating the charge recovery time.